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Originally named 3GIO technology by the Intel Developer Forum (IDF) in 2001 it was eventually renamed as PCI Express. The 1.0 version of the PCI Express was approved on July 23, 2002.

The PCI express architecture is a low pin-count, highly scalable, general-purpose serial I/O interconnect. It will provide a standard for various I/O solutions to be consolidated within a system platform. For example, PCI Express can be used as an alternative to the existing PCI, AGP and core logic interconnects simplifying architecture and reducing system components. This point-to-point architecture is designed to address the needs of multiple market segments in both the computing and communication industries. It offers a scalable bandwidth up to 8 gigabytes per second. It supports scalable lanes with the following widths: 1, 2, 4, 8, and 16. This allows different card sizes to be used within the same system. Also multiple different link speeds allow bandwidth ranging from 2.5Gbit/s to 160Gbit/s.

Key features:

• Complete backwards compatibility and interoperability with existing PCI drivers.
• RASM support: This includes error handling and correction, power management, Quality of Service(QoS), isochrony, hot swap and hot plug, peer-to-peer support, and extended configuration attributes.
• Layered architecture enabling physical layer attachment to copper, optical, or emerging physical signaling media to allow for future encoding schemes.
• Maximum bandwidth per pin to enable unique and small form factors, simplify board design and routing, and reduce signal integrity issues.
• Embedded clocking scheme enables extensive frequency scalability.
• Bandwidth scalability with frequency and/or interconnect width.
• Mechanisms to support embedded and communications applications

To learn more about PCI Express, visit the following website:

  www.pcisig.com